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RT8065 ? ds8065-07 november 2012 www.richtek.com 1 ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. applications z lcd tv and monitor z notebook computers z distributed power systems z ip phones z digital cameras general description the RT8065 is a high efficiency synchronous, step-down dc/dc converter. its input voltage range is from 2.7v to 5.5v and provides an adjustable regulated output voltage from 0.8v to 5v while delivering up to 3a of output current. the internal synchronous low on-resistance power switches increase efficiency and eliminate the need for an external schottky diode. the default switching frequency is set at 2mhz, if the rt pin is left open. it can also be varied from 200khz to 2mhz by adding an external resistor. current mode operation with external compensation allows the transient response to be optimized over a wide range of loads and output capacitors. ordering information 3a, 2mhz, synchronous step-down converter note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. features z z z z z high efficiency : up to 95% z adjustable frequency : 200khz to 2mhz z z z z z no schottky diode required z z z z z 0.8v reference allows low output voltage z z z z z low dropout operation : 100% duty cycle z z z z z enable function z z z z z external soft-start z z z z z power good function z z z z z rohs compliant and halogen free RT8065zsp : product number ymdnn : date code RT8065zsp marking information RT8065 zspymdnn RT8065zqw 29 : product code ymdnn : date code 29 ym dnn package type sp : sop-8 (exposed pad-option 2) qw : wdfn-8l 3x3 (w-type) RT8065 lead plating system z : eco (ecological element with halogen free and pb free)
RT8065 2 ds8065-07 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit table 1. recommended components selection for f sw = 1mhz v out (v) r1 (k ) r2 (k ) r comp (k ) c comp (pf) l ( h) c out ( f) 3.3 75 24 33 560 2 22 2.5 51 24 22 560 2 22 1.8 30 24 15 560 1.5 22 1.5 21 24 13 560 1.5 22 1.2 12 24 11 560 1.5 22 1 6 24 8.2 560 1.5 22 vin RT8065 v in 2.7v to 5.5v rt lx comp fb gnd r osc l c out r comp v out c in 10f c comp r1 r2 ss c ss 10nf chip enable r3 100k pgood pgood en 4 8 6 3 2 9 (exposed pad) 1 7 5 pin configurations (top view) sop-8 (exposed pad) comp ss en vin pgood fb lx rt gnd 2 3 4 5 6 7 8 9 comp ss vin pgood fb rt lx en 7 6 5 1 2 3 4 8 gnd 9 wdfn-8l 3x3
RT8065 3 ds8065-07 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram functional pin description pin no. sop-8 (exposed pad) wdfn-8l 3x3 pin name pin function 1 1 comp error amplifier compensation point. the current comparator threshold increases with this control voltage. connect external compensation elements to this pin to stabilize the control loop. 2 2 ss soft-start control input. connect a capacitor from ss to gnd to set the soft-start period. a 10nf capacitor sets the soft-start period to 800 s (typ.). 3 3 en enable control input. float or connect this pin to logic high for enable. connect to gnd for disable. 4 4 vin power input supply. decouple this pin to gnd with a capacitor. 5 5 lx internal power mosfet switches output. connect this pin to the inductor. 6 6 rt oscillator resistor input. connect a resistor from this pin to gnd sets the switching frequency. if this pin is floating, the frequency will be set at 2mhz internally. 7 7 fb feedback. receives the feedback voltage from a resistive divider connected across the output. 8 8 pgood power good indicator. this pin is an open drain logic output that is pulled to ground when the output voltage is not within 12.5% of regulation point. 9 (exposed pad) 9 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. driver nisen control logic n-mosfet i lim 0.7v 0.4v isen slope com osc output clamp 0.8v enable otp comp rt fb vin gnd sd lx uv p-g hiccup oc limit en ss 10a ea pgood
RT8065 4 ds8065-07 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. absolute maximum ratings (note 1) z supply input v oltage, vin ----------------------------------------------------------------------------------------- ? 0.3v to 6v z lx pin switch voltage ---------------------------------------------------------------------------------------------- ? 0.3v to (v in + 0.3v) <10ns ------------------------------------------------------------------------------------------------------------------ ? 5v to 8.5v z other i/o pin v oltages --------------------------------------------------------------------------------------------- ? 0.3v to (v in + 0.3v) z lx pin switch current ---------------------------------------------------------------------------------------------- 5a z power dissipation, p d @ t a = 25 c sop-8 (exposed pad) -------------------------------------------------------------------------------------------- 1.333w wdf n-8l 3x3 -------------------------------------------------------------------------------------------------------- 1.429w z package thermal resistance (note 2) sop-8 (exposed pad), ja ---------------------------------------------------------------------------------------- 75 c/w sop-8 (exposed pad), jc --------------------------------------------------------------------------------------- 15 c/w wdfn-8l 3x3, ja --------------------------------------------------------------------------------------------------- 70 c/w wdfn-8l 3x3, jc --------------------------------------------------------------------------------------------------- 8.2 c/w z junction temperature ----------------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ---------------------------------- --------------------------------------- 260 c z storage temperature range -------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body model) ---------------------------------------------------------------------------------------- 2kv electrical characteristics (v in = 3.3v, t a = 25 c, unless otherwise specified) recommended operating conditions (note 4) z supply input voltage, vin ----------------------------------------------------------------------------------------- 2.7v to 5.5v z junction temperature range -------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range -------------------------------------------------------------------------------------- ? 40 c to 85 c parameter symbol test conditions min typ max unit feedback reference voltage v ref 0.784 0.8 0.816 v active , v fb = 0.78v, not switching -- 460 -- dc bias current shutdown -- -- 10 a output voltage line regulation v in = 2.7v to 5.5v -- 0.1 -- %/v output voltage load regulation 0a < i load < 3a -- 0.25 -- % error amplifier trans-conductance gm -- 400 -- a/v current sense trans-resistance r t -- 0.3 -- r osc = 330k 0.8 1 1.2 switching frequency switching 0.2 -- 2 mhz logic-high v ih 1.6 -- -- en input voltage logic-low v il -- -- 0.4 v
RT8065 5 ds8065-07 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max unit switch on-resistance, high r ds(on)_p i lx = 0.5a -- 120 180 m switch on-resistance, low r ds(on)_n i lx = 0.5a -- 80 120 m peak current limit i lim 3.6 4.5 -- a v in rising -- 2.4 -- under voltage lockout threshold v in falling -- 2.2 -- v rt shutdown threshold v rt v rt rising -- v in ? 0.7 v in ? 0.4 v soft-start period t ss c ss = 10nf -- 800 -- s pgood trip threshold -- 87.5 -- %v out
RT8065 6 ds8065-07 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 output current (a) efficiency (%) v in = 5v, v out = 1.1v, i out = 0a to 3a switching frequency vs. temperature 0.94 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 -50 -25 0 25 50 75 100 125 temperature (c) switching frequency (mhz) 1 v in = 5v, v out = 1.1v, i out = 0.6a, r rt = 330k reference voltage vs. temperature 0.76 0.77 0.78 0.79 0.80 0.81 0.82 0.83 0.84 -50 -25 0 25 50 75 100 125 temperature (c) reference voltage (v) v in = 5v, v out = 1.1v efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 output current (a) efficiency (%) v in = 5v, v out = 3.3v, i out = 0a to 3a output voltage vs. output current 1.070 1.080 1.090 1.100 1.110 1.120 1.130 0 0.5 1 1.5 2 2.5 3 output current (a) output voltage (v) v in = 5v, v out = 1.1v, i out = 0a to 3a output voltage vs. output current 3.300 3.310 3.320 3.330 3.340 3.350 3.360 00.511.522.53 output current (a) output voltage (v) v in = 5v, v out = 3.3v, i out = 0a to 3a
RT8065 7 ds8065-07 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. switching time (500ns/div) v out (10mv/div) v lx (5v/div) v in = 5v, v out = 3.3v, i out = 3a switching time (500ns/div) v out (10mv/div) v lx (5v/div) v in = 5v, v out = 1.1v, i out = 3a load transient response time (100 s/div) i out (1a/div) v out (200mv/div) v in = 5v, v out = 3.3v, i out = 1a to 3a, r comp = 33k , c comp = 560pf load transient response time (100 s/div) i out (1a/div) v out (200mv/div) v in = 5v, v out = 1.1v, i out = 1a to 3a, r comp = 10k , c comp = 560pf v in uvlo vs. temperature 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 -50 -25 0 25 50 75 100 125 temperature (c) v in uvlo (v) rising falling enable voltage vs. temperature 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 -50 -25 0 25 50 75 100 125 temperature (c) enable voltage (v) rising falling
RT8065 8 ds8065-07 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. power off from en time (250 s/div) v en (5v/div) v out (2v/div) v pgood (5v/div) i out (5a/div) v in = 5v, v out = 1.1v, i out = 3a power on from en time (500 s/div) v en (5v/div) v out (2v/div) v pgood (5v/div) i out (5a/div) v in = 5v, v out = 1.1v, i out = 3a power on from v in time (2.5ms/div) v in (5v/div) v out (1v/div) v pgood (10v/div) i out (2a/div) v in = 5v, v out = 1.1v, i out = 3a, en = high power off from v in time (5ms/div) v in (5v/div) v out (1v/div) v pgood (10v/div) i out (2a/div) v in = 5v, v out = 1.1v, i out = 3a, en = high
RT8065 9 ds8065-07 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information the basic ic application circuit is shown in typical application circuit. external component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by c in and c out . main control loop during normal operation, the internal upper power switch (p-mosfet) is turned on at the beginning of each clock cycle. current in the inductor increases until the peak inductor current reaches the value defined by the output voltage (v comp ) of the error amplifier. the error amplifier adjusts its output voltage by comparing the feedback signal from a resistive voltage-divider on the fb pin with an internal 0.8v reference. when the load current increases, it causes a reduction in the feedback voltage relative to the reference. the error amplifier increases its output voltage until the average inductor current matches the new load current. when the upper power mosfet shuts off, the lower synchronous power switch (n-mosfet) turns on until the beginning of the next clock cycle. output voltage setting the output voltage is set by an external resistive voltage divider according to the following equation : out ref r1 v = v 1 + r2 ?? ?? ?? where v ref equals to 0.8v typical. the resistive voltage divider allows the fb pin to sense a fraction of the output voltage as shown in figure 1 fb gnd r1 r2 RT8065 v out figure 1. setting the output voltage soft-start the ic contains an external soft-start clamp that gradually raises the output voltage. the soft-start timing is programmed by the external capacitor between ss pin and gnd. the chip provides an internal 10 a charge current for the external capacitor. if 10nf capacitor is used to set the soft-start, the period will be 800 s (typ.). power good output the power good output is an open-drain output and requires a pull up resistor. when the output voltage is 12.5% above or 12.5% below its set voltage, pgood will be pulled low. it is held low until the output voltage returns to within the allowed tolerances once more. during soft-start, pgood is actively held low and is only allowed to transition high when soft-start is over and the output voltage reaches 87.5% of its set voltage. operating frequency selection of the operating frequency is a tradeoff between efficiency and component size. higher frequency operation allows the use of smaller inductor and capacitor values. lower frequency operation improves efficiency by reducing internal gate charge and switching losses but requires larger inductance and/or capacitance to maintain low output ripple voltage. the operating frequency of the ic is determined by an external resistor, r osc , that is connected between the rt pin and ground. the value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator. the practical switching frequency ranges from 200khz to 2mhz. however, when the rt pin is floating, the internal frequency is set at 2mhz. determine the rt resistor value by examining the curve below. please notice the minimum on time is about 90ns.
RT8065 10 ds8065-07 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current, i l , increases with higher v in and decreases with higher inductance. out out l in vv i = 1 fl v ?? ?? ?? ?? ?? ?? ?? having a lower ripple current reduces not only the esr losses in the output capacitors but also the output voltage ripple. highest efficiency operation is achieved by reducing ripple current at low frequency, but attaining this goal requires a large inductor. for the ripple current selection, the value of i l = 0.4(i max ) is a reasonable starting point. the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below a specified maximum value, the inductor value needs to be chosen according to the following equation : out out l(max) in(max) vv l = 1 fi v ??? ? ? ??? ? ??? ? ??? ? using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. slope compensation and peak inductor current slope compensation provides stability in constant frequency architectures by preventing sub- harmonic oscillations at duty cycles greater than 50%. it is accomplished internally by adding a compensating ramp to the inductor current signal. normally, the peak inductor current is reduced when slope compensation is added. for the ic, however, separated inductor current signal is used to monitor over current condition, so the maximum output current stays relatively constant regardless of the duty cycle. hiccup mode under voltage protection a hiccup mode under voltage protection (uvp) function is provided for the ic. when the fb voltage drops below half of the feedback reference voltage, v fb , the uvp function is triggered to auto soft-start the power stage until this event is cleared. the hiccup mode uvp reduces the input current in short circuit conditions, but will not be triggered during soft-start process. under voltage lockout threshold the RT8065 includes an input under voltage lockout protection (uvlo) function. if the input voltage exceeds the uvlo rising threshold voltage, the converter will reset and prepare the pwm for operation. however, if the input voltage falls below the uvlo falling threshold voltage during normal operation, the device will stop switching. the uvlo rising and falling threshold voltage has a hysteresis to prevent noise-caused reset. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the figure 2. switching frequency vs. rt resistor 0.0 0.4 0.8 1.2 1.6 2.0 2.4 0 300 600 900 1200 1500 1800 2100 r rt (k ) switching frequency (mhz) 1
RT8065 11 ds8065-07 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 3. derating curve of maximum power dissipation layout considerations follow the pcb layout guidelines for optimal performance of the ic. ` connect the terminal of the input capacitor(s), c in , as close to the vin pin as possible. this capacitor provides the ac current into the internal power mosfets. ` lx node experiences high frequency voltage swings so should be kept within a small area. ` keep all sensitive small signal nodes away from the lx node to prevent stray capacitive noise pick up. ` connect the fb pin directly to the feedback resistors. the resistive voltage-divider must be connected between v out and gnd. figure 4. pcb layout guide comp ss en vin pgood fb lx rt gnd 2 3 4 5 6 7 8 9 place the compensation components as close to the ic as possible v out gnd r2 r1 v in c in c out v out l1 r comp c comp lx should be connected to inductor by wide and short trace, and keep sensitive components away from this trace place the feedback resistors as close to the ic as possible place the input and output capacitors as close to the ic as possible gnd r osc gnd c ss maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for sop-8 (exposed pad) packages, the thermal resistance, ja , is 75 c/w on a standard jedec 51-7 four-layer thermal test board. for wdfn-8l 3x3 packages, the thermal resistance, ja , is 70 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a =25 c can be calculated by the following formulas : p d(max) = (125 c ? 25 c) / (75 c/w) = 1.333w for sop-8 (exposed pad) package p d(max) = (125 c ? 25 c) / (70 c/w) = 1.429w for wdfn-8l 3x3 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curves in figure 3 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. place the compensation components as close to the ic as possible v out gnd r2 r1 v in c in c out v out l1 r comp c comp lx should be connected to inductor by wide and short trace, and keep sensitive components away from this trace place the feedback resistors as close to the ic as possible place the input and output capacitors as close to the ic as possible gnd r osc comp ss vin pgood fb rt lx en 7 6 5 1 2 3 4 8 gnd 9 gnd c ss 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb sop-8 (exposed pad) wdfn-8l 3x3
RT8065 12 ds8065-07 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. outline dimension a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 x 2.000 2.300 0.079 0.091 option 1 y 2.000 2.300 0.079 0.091 x 2.100 2.500 0.083 0.098 option 2 y 3.000 3.500 0.118 0.138
RT8065 13 ds8065-07 november 2012 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 d 2.950 3.050 0.116 0.120 d2 2.100 2.350 0.083 0.093 e 2.950 3.050 0.116 0.120 e2 1.350 1.600 0.053 0.063 e 0.650 0.026 l 0.425 0.525 0.017 0.021 w-type 8l dfn 3x3 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options d 1 e a3 a a1 d2 e2 l b e see detail a

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